Tohoku University and the automotive supplier Aisin have demonstrated a 16nm AI system on chip that starts its operating system 65.7 milliseconds after power-on, with no external DRAM or SSD needed for the AI processing system, according to a joint release published on 2 November 2026.

The chip carries 32MB of embedded STT-MRAM, spin-transfer-torque magnetic random access memory, on the same die as the processor. Boot data for the operating system sits in that memory alongside the weights of the AI model, so neither has to be transferred in from external storage when the power comes on.

Measured against a conventional design, the releases put the boot speed-up at 38.59 times, which the bullet summaries round to about 39 times. AI processing time was 10.16 times shorter, and the system as a whole was 25.2 times faster.

The work was done by a team at Tohoku University’s Center for Innovative Integrated Electronic Systems, led by Professor Tetsuo Endoh, together with a team from Aisin Corporation. The named authors are Tetsuo Endoh, Takanobu Naruse, Tao Li, Shoji Ikeda, Mitsuo Yasuhira and Hiroshi Yamada.

Where the 65.7 milliseconds comes from

Edge AI hardware normally boots the slow way. The releases describe the problem directly: at power-on, the operating system and the AI model have to be read in from external memory, and they name that loading step as one of the reasons AI systems take time to start.

STT-MRAM is non-volatile, so it holds its contents with the power off. The Tohoku glossary note says the memory stores information using the magnetisation state of a magnetic material, that it keeps leakage power low in standby, and that reads and writes are fast.

Putting 32MB of it on the die removes the need to transfer large amounts of data from an external SSD or DRAM at startup.

The design is described as near-memory computing, which the release defines as placing memory close to the processor or AI accelerator so data travels a shorter distance, cutting the power spent moving it. In this chip the AI accelerator reads model weights directly out of the on-die STT-MRAM, which the release says reduces both the delay and the energy associated with data transfer.

That is also why the second number matters. With no weight transfer from external memory, the release puts object detection and similar AI work at roughly one tenth of the time taken by the conventional approach.

Tiny YOLOv3 at 50.7 mJ per frame

The demonstration workload is Tiny YOLOv3, a cut-down version of the YOLO object detector, which identifies the type and position of objects in an image. The release says it was used to show AI processing of the kind intended for edge equipment.

Fitting that model inside the limited on-chip STT-MRAM capacity took two measures. The chip uses an 8/16-bit hybrid multiplication architecture, and the team applied weight sharing, which the release says made object detection with Tiny YOLOv3 possible within that limited on-chip capacity.

Energy for one frame of object detection came out at 50.7 mJ. The releases give that as one fiftieth of the conventional figure.

The full paper title, as listed by Tohoku University, is “A 65.7ms Quick-instant-on and 50.7mJ/frame Tiny YOLOv3-based Object-detection 16nm-AI-SoC with 32MB-embedded-MRAM and Hybrid-multiplication-architecture”.

A conference chip, not a product

The releases say the results were to be presented at the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2026, held from 1 to 4 November in Hsinchu, Taiwan. The Tohoku page illustrates the work with a die photograph, a key metrics summary table and a demonstration system, which is the usual shape of a conference silicon result rather than a shipping part.

Nothing in either release describes a product, a price, a customer or a production schedule.

The stated target is edge devices. Both releases open by saying that AI techniques such as generative AI and image recognition are spreading quickly into cars, robots, cameras and IoT equipment, and that growing model sizes make memory access and transfers to and from external memory a drag on speed and energy efficiency.

Aisin, which supplies components to the car industry, is the industrial partner on the paper, and that list of target devices is the framing both releases use. It is worth being precise about what the headline number covers: the releases describe 65.7 milliseconds as the time from power-on to OS startup, and their headlines phrase it as starting the object-detection AI module that fast. Neither release gives a figure for how long the chip takes to produce its first detection after being switched on.

Both the Tohoku and Aisin pages headline the chip with the phrase 世界初, world first, for a 16nm AI SoC carrying STT-MRAM. The measured figures in the releases are the boot time of 65.7 milliseconds, the 38.59 times boot speed-up, the 10.16 times reduction in AI processing time, the 25.2 times system-level reduction and the 50.7 mJ per frame energy figure, all given against an unnamed conventional approach.

The releases do not identify the conventional system used as the baseline, and they do not compare the chip with other embedded MRAM parts. What they do specify is the combination on this die: a 16nm FinFET AI SoC holding 32MB of embedded STT-MRAM, with both an operating system image and a neural network’s weights stored in it.

Part of the work was carried out under a consignment from Japan’s national research and development agency, the New Energy and Industrial Technology Development Organization, or NEDO.

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